In a board which employs an A/D or D/A converter and processes digital signals by DSP, a plurality of clocks supplied from a clock source through a clock driver have different phases and characteristics according to a clock pattern path to destination. Accordingly, the DSP latching data significantly affects the entire signal-to-noise ratio (SNR) or performance depending on what kind of clock is used.
The elements that change a clock's characteristic and delay in a conventional development are divided into three elements. The first element is values of R, L and C. The second element is a driver delay. The third element is a characteristic change by elements peripheral to pattern that a clock passes. These three elements are difficult to change once they are designed and a printed circuit board (PCB) is manufactured.
In this regard, a developer has to inevitably expend extensive costs and time since he must manufacture a plurality of PCBs. Furthermore, the developer is severely inconvenienced as he must change the values of R, L and C elements directly whenever any delicate external changes occur.
More specifically, this is because a clock characteristic and a board which employs an A/D or D/A converter and processes digital signals by DSP must change and test a clock element until a desired specification is obtained in order to design and manufacture the board. Therefore, a plurality of PCBs must be manufactured and be tested whenever each element changes.
Further, the characteristics of the PCBs tend to change due to the manufacturing environment although the PCBs of a desired specification are intended. Therefore, a delicate difference from one board to another board may be overcome by changing the values of R, L and C elements in order to optimize the characteristic change.
For the above reasons, a developer must expend significant costs and time since he must manufacture a plurality of PCBs and change the values of R, L and C elements directly whenever the delicate external changes are encountered.